Generator for variable and repetitive sequences of digital words



Filed Sept. 28, 1964 Nov. 14, 1967 D. J. CHESAREK ET AL GENERATOR FOR VARIABLE AND REPETITIVE] SEQUENCES OF DIGITAL WORDS '7 Sheets-Sheet 1 CLOCK smm SOURCE i 4 w /L/Tu'um BITPERIOD an COUNTER LOGICAL NETWORK 1o REGISTER 20 smmcmcunm (Pi-P6) P64 FPS-"1W1 wean COUNTER WORDS PRESET FROM REGISTER g REGISTER36 -f0PERATORS (Vii-W4) a (Hi-R4] CONSOLE CI PF F w T 31 5? 3* CYCLE courmza CYCLES PRESET REGISTER 2 5 REGISTER 15 (01-05) (Ti-T5) WNW w T155 59 T EGSTERA REGISTERB R 1 uu-m 2 MATR'XLZ 54 (81-84) A A A A 81H 81 B 21 31 a 1 2 5 4 OUTPUTTO OPERATOR'S 52 28 26 CONSULE REGISTER A MATRIX 12 PRESET 4 5 PRESET g FROM OPERATOR'S CONSOLE FIG. 1 INVENTORS ATTORNEY Nov. 14, 1967 0. J. CHESAREK ET AL 3,353,157

GENERATOR FOR VARIABLE AND REPETITIVE SEQUENCES OF DIGITAL WORDS R-S FLIP-FLOP AI A1 "I u III m I INDICATES TRIGGERING OF THE INPUT. FIGZ AI x x No CHANGE x INDICATES N0 TRIGGERING OF THE INPUT.

X FALSE INDICATES AN INDETERMINATE STATE; IF B I I X TRUE SIMULTANEOUS INPUTS ARE TO BE AVOIDED.

I I I R-S-T FLIP-FLOP BI 1 9i & l 3 I' x x x no CHANGE x x I IF TRUE, GOES FALSE; IF FALSE,GOES TRUE. F |G.3 I I I FI sE I Obi I x x TRUE t I I x I I I x I I I Nov. 14, 1967 D.J.CHESAREK ETAL GENERATOR FOR VARIABLE AND REPE'II'IIVE SEQUENCES OF DIGITAL woans 7 Sheets-Sheet 5 Filed Sept. 28, 1964 8-4-2-1 DECIHAL REPR NTATION ol o ool-io wwwwa B888 FIG] FIG.6

Nov. 14, 1967 0. J. CHESAREK ET AL 3,353,157

GENERATOR FOR VARIABLE AND REPETITIVE SEQUENCES OF DIGITAL. WORDS Filed Sept. 28, 1964 7 Sheets-Sheet 4.

NON-SHIFT REGISTER B C U O 0 43 W BB N2 1 1 4mm l-VA ZJ I 4 2 2 4 2 4 2 4 3 4 20 4 4 5 M B B M B B 8 B B B B B B B DU 8 B BB .1. W 11M 5 51.13 1 1 3 1 1 1213 11 123 123 1 123 1 13 El m m m B B B B B Du B Du Du Du B B Du 8 8 B H. B Du B B B B B B 00 Du B B B 8 8 Ru m z a I z a s s s fl=1 a HP 1nd A". Luv A? 121d 1| 7J4 1234 1234 254 1254 125 1 4 1 0 5 9 6 0 0 13 r3 0 6 9 5 5 6 61 21 I11 I. 1 1 1 1 2 5 5 0 2 w. 5 w O 1 11 1 1| .1 .1 0 0w 6 p 1 11 w A 1 o 1 1 1 2 \I 1 1 8 9 I 2 H 0 1 7 2 r0 1 1 1 D 1 5 1 2 0 N 1 I 1 1 4 1 CL 00 1 1 1 A 1 11 4 4 R 4 0 11 1 U 1 1 1 1 4 6 w flu G 9 4 1 1 S 1 0 C1 .1 2 J1 0 4 Mm. 1.. 11 0 W H1 1 1 n U .1 .1 1 G M .1 N 1 4 1 6 H .1 .1 1 w 2 .1 1 1 1 70 2 4 1 1 9 1 2 0 N 1 .1 .1 H 1 1 n0 1 2 .1 E 1 1 1S 8 2 1 5 1 C T ll 0 1 1 5 1 1 N N 1 1 .1 I1 1 M 1 W rm .1 4 w 1 6 1 H 1 1 H I11 4 3 1 5 m 6 9 1 1 1 .1 .1 5 w 11 T 1 I I S 1 1 1 NW 1 1 5 mm 00 T T 1 4 4 .1 1 1 5 1 1 l 1 5 1 1 Nov. 14, 1967 D. J. CHESAREK ET AL 3,353,157

GENERATOR FOR VARIABLE AND REPETITIVE SEQUENCES OF DIGITAL WORDS 7 Sheets-$heet 6 Filed Sept. 28 1964 Nov. 14, 1967 Filed Sept. 28, 1964 D. J. CHESAREK ET AL 7 Sheets-Shee t '7 PRESETS REGISTER CONTENT CYCLES WORDS A CYCLE WORD BIT l i ll Q 5 A ii A i.

21 9 I4 0 W P1 T00 0000 P2 OIIO P3 I000 P4 IOII P5 IOII P5 IOII W2 P1 IOII 0000 P2 OIIO P3 OIIO P4 OIGI F5 IOOI P6 IOOI 01 P1 IOOIOOOO P2 OIIO P3 OIIO P4 0H0 P5 IOIO P IOIO I I 1 I I I I I I F I I I I I I I W9 P IIII 0000 Pg 0H0 P3 I000 P4 IOII P5 0m P6 0m 0 01 P1 m0 0000 P2 OIIO P3 I000 P4 IOII P5 IOII I I 0 I I I I I 021 W9 P1IIIIOOO0 P2 0H0 P I000 P4 IOII P5 0111 P6 0111 ACTIVITY REGISTER A FOLLOWS PRESETIS, MATRIX I2 IS ACTIVATED ACCORDING TO PRESET I3 CONSOLE. REGISTER A FOLLOWS REGISTER FIRST WORD APPEARS AT OPERATORS B. REGISTER B IS RESET.

LAST WORD APPEARS ATOPERATOR'S 0002000 00000000 02 E005 SIGNAL. IREGISTER A FOLLOWS PRESET I5.

52 IS SET. SIGNAL C IS CUT OFF.

FIG.II

United States Patent Ofilice 3,353,157 Patented Nov. 14, 1967 3,353,157 GENERATOR FOR VARIABLE AND REPETTTIVE SEQUENCES OF DIGITAL WORDS Donald J. Chesarek, San Jose, and Harold E. Petersen,

Saratoga, Calif., assignors to International Business Machines Corporation, New York, N.Y., a corporation of New York Filed Sept. 28, 1964, Ser. No. 399,598 7 Claims. (Cl. 340-1725) ABSTRACT OF THE DISCLOSURE A digital word generator operable through computer control of a network of logical gates and including a pair of registers in which words are set up in a sequence established by the network, the first word, number of words and the number of sequences also being established by the network as accordingly arranged by switch matrices available to the operator of the computer.

This invention relates to a digital word generator and, more particularly, to a generator which utilizes digital techniques to produce series of multi-bit words, each word bearing a designated relationship to the others, said relationship capable of being changed.

Word generators, as used in the switching and computer arts, are employed usually to establish a unique combination of bits (i.e., words) for each of a plurality of inputs signals (clock pulses). The number of bit combinations and their relationship is determined by the number of stages in the generator and by the logical network which provides the interconnections between the stages. As an illustration, a three-stage register in which the stages comprise any of the well known bistable-state circuits (flip-flops), may be considered. The two inputs and two outputs for each flip-flop may feed into a logical network which interconnects them to provide, for repetitive clock pulse input (i.e., during sequential bit periods of operation), a counting sequence of all eight words available from a three-stage register, an abbreviated counting sequence (e.g., five words followed by reset to the first word), a shift sequence of maximum length or less, etc. With particular respect to the generation of maximum-length shift sequences, designated in the error checking art as m-sequences, the logical network for the threestage register B, comprising fiip-fiops B1, B2, B3 (nomenclature to be explained later), may be arranged such that the input of first stage B1 is the exclusive OR function of the output of second and third stages B2 and B3, Whereas second stage B2 follows first stage B1 and third stage B3 follows second stage B2. This may be represented by the set of Boolean application equations: B1=B269B3, B2=B1, 83:32. The register, when preset with any word except 000 (this word may be considered as comprising a trivial sequence or static count) and repetitively excited by clock pulses, will sequentially generate all seven possible different words (except 000), 111, 011, 001, 100, 010, 101, 110, and then repeat.

On the other hand, the logical network may be arranged such that the input to first stage B1 is the equals" function of the outputs of stages B2 and B3, the other two stages being connected as before: 81:32 @BS, B2=Bl, B3=B2. In this case also, the register, when preset with any word except 111 (the static count) and repetitively excited by clock pulses, will sequentially generate all seven words (except 111), but in a different order, 000, 100, 110, 011, 101, 010, 001, and then repeat. These two sequences will be recognized as complemetary.

It will also be noted that the above two logical network arrangements cause stage B1 to operate as a summer stage since it indicates the result of the modulo 2 addition of the content of other stages of the register.

Further, by arranging the logical network to connect the register as represented by the application equations B1=B1EBB3, B2=Bl, 83:32, the m-sequence 111, 011, 101, 010, 001, 100, (static count 000) is obtained, and, by arranging the logical network to connect the register as represented by the equations B1=B1 @B3, BZ=B1, B3=B2, the m-sequence 000, 100, 010, 101, 110, 011, 001 (static count 111) is obtained. These two sequences are also recogized as complementary.

It will be noted that the last two logical network arrangements cause stage B1 to operate as an accumulator stage since it indicates the result of a modulo 2 addition of the content of at least one other stage to its own prior content.

It is additionally interesting to note that the logical network B1=B1G3B2, B2=B1, B3=B2 yields the short cycle 011, 101, 110 and the logical network B1=B1 @132, B2:B1, B3:B2 yields the Complementary cycle 100, 010, 001 and it is possible that, in registers comprising a greater number of stages, networks corresponding to other logical connectors may yield additional counting sequences, cyclic or otherwise.

It has been customary in the past to arrange the logical network in contemplation of the sequential outputs it is desired to obtain. Thus, in a digital data transmission system in which capability to check single errors is to be included, selection of bit positions to be checked by the individual check bits which will accompany the message bits may be made in accordance with an m-sequence. Such systems therefore may include m-sequence generators in both the transmitter and receiver. If the transmission fidelity should indicate the desirability of enhancing the error checking ability of the system to the handling a burst errors, or of the desirability of handling messages of greater length, some means must be provided to replace the m-sequence generators with ones of increased size. This has required a major alteration in station equipment, usually at considerable expense and system inactivity. It is an object of this invention to provide a word generator sufficiently versatile in construction so as to avoid these disadvantages.

It is another object of this invention to provide a word generator the internal logical network of which enables selective alteration of the word sequence output within a Wide range of sequences, both of a full number of words or a reduced number of words, thereby lending usefulness in counting, selecting, indicating, security of data transmitted over shared communications links, security of shared memories and other applications.

It is still another object of this invention to present an approach to the construction of binary counters and word generators characterized by simplicity of logic and the production, where required, of a maximum number of unique outputs for the equipment used.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawmgs.

FIGURE 1 is a generic block diagram into which the word generator of the present invention fits;

FIGURE 2 is the block diagram representation and truth table depicting the logic of an RS bistable state circuit, used in the embodiment of the invention shown in FIGURES 10a and 10b.

FIGURE 3 is the block diagram representation and truth table depicting the logic of an R-S-T bistable state circuit, also used in the embodiment of the invention shown in FIGURES 10a and 10b;

FIGURES 4, 5, 6, and 7 are tables depicting typical sequences of words, in binary and decimal representation, available from the word generator of FIGURES a and 10b when its changeable matrix is set up in accordance with the logic (application equations) given with each table;

FIGURE 8 is a table depicting cyclic word sequences available from the word generator of FIGURES 10a and 10b when its changeable matrix is set up in accordance with the indicated logic, for which register B is a shift register;

FIGURE 9 is a table depicting some of the cyclic word sequences available from the word generator FIGURES 10a and 10b when its changeable matrix is set up in accordance with the indicated logic, for which register B is not a shift register;

FIGURES 10a and 10b together form a schematic diagram of a word generator according to the invention and having its changeable matrix preset to produce the specific maximum length cyclic shift sequence of 4-bit words according to the logic of FIGURE 6, and employing RS and RS-T flip-flops in its registers; and

FIGURE 11 comprises a tabulation of some of the activity of the example of the system given in FIGURE 10 when preset as indicated.

The present invention contemplates the integration of the aforementioned word generation technique into a computer system capable of storing numbers as combinations of true and false states in a set of bistable state circuits such as flip-flops, as bistate magnetic recordings on a magnetizable surface, as the two states of remanent magnetization of magnetic cores, or as some other well known form (i.e., mechanization) of binary representation, and involves the sequential operation of what has come to be recognized as computer structure, including pulse sources, AND gates, OR gates, etc. Very generally, the system of the present invention may be regarded as comprised of bistable-state circuits, a source of clock signals for synchronization, a clock signal counter to indicate time periods during which the system outputs may be recognized, various other counters, switch means to preset portions of the system and a logical network capable of responding to and controlling the operation of the combination of components to be described. This generic representation is shown in FIGURE 1, which, for the purposes of this specification, contemplates the generation of 4-bit words and employs a pair of 4-stage registers, designated as registers A and B, connected to logical network 10. Logical network 10 is operative to enter information into, remove information from, and sequence the operation of registers A and B such that the combination comprises a word generator, as distinguished from other equipment, the output Words being available (from register B) on line 26 as indicated, which, as with other lines in the system, comprises a plurality of conductors, in this case, designated B B B and B A portion of logical network 10, namely, matrix 12, is changeable, i.e., its configuration, and consequently the logic it contributes, may be altered by an operator; this is represented by preset circuit 13 which connects to matrix 12 by line 22. Also available to the operator is preset circuit 15 connecting by line 24 to register A, in which a particular first word may be set up for subsequent transfer to and read-out from register B.

Although the inventive concept is quite applicable to other systems of representing information in a computer, it will be presented herein with regard to a synchronized pulse system. By this is meant a system in which repetitive pulses, whether information representing, or clock signals, or otherwise, are synchronized to occur at particular time intervals with reference to each other. In such a system, signals may be of square wave shape alternating between specific voltage levels; and it is most convenient to regard synchronization as being provided by clock signals of symmetrical square wave shape generated by a pulse generator, which may comprise a repetitive magnetic recording associated with a sensing electromagnetic transducer and pulse shaping circuitry, or a frequency controlled square wave generator, or other appropriate means. Synchronization by such means implies that the potential of a line may change between the voltage levels only at the time of the trailing edge of the clock signal pulse, the time between trailing edges being designated as a bit period.

In FIGURE 1, the aforementioned bit periods are es tablished by clock signal source 14 which emits symmetrical square wave signal C on line 16; through logical network 10, lines connecting to line 61 provide signal C input to all gates.

It is appropriate, before going into a description of the details of the circuitry of the invention as applied to specific examples, to describe the convention employed herein for nomenclature.

The circuits of the invention are used to perform logical operations (AND, OR, etc.) and are represented in the form of equations shown in Boolean notation. The terms of the equations are mechanized in circuitry by output signals from flip-flops, single-shots and switches, which are electronic devices having two possible steady state conditions. One of these conditions is referred to as true or set and the other condition is referred to as false" or reset; when for instance, a flip-flop is described as being true or set, it will be understood to be storing a binary digit one (bit 1), and when it is described as a false or reset, it will be understood to be storing a binary digit zero (bit 0).

Input signals to the flip-flop are supplied by gates and output signals from the flip-flop are supplied to similar gates. These gates comprise logical network 10 and it is their operation that is described by means of Boolean equations, each of which thus defines the triggering of the bistable circuit. The terms of an equation correspond to output signals and the equation represents the activation of gates and, consequently, the generation of input signals, during the aforementioned bit periods, triggering actually occurring at the end of the bit period, so that the circuits are in the desired states during the next bit period.

The nomenclature used for the present invention employs combinations of letters and numbers for designating the terms of the equations. The bistable circuits themselves are designated by combinations of capital letters and numbers: thus, flip-flops A1, B3, etc. The output signals of the flip-flop are complementary, and one is characterized by a corresponding capital letter with the associated number shown as a subscript: thus, signals A B etc.; the other is accompanied by an aflixed prime: thus, signals A,', B etc. It will be understood that, in circuitry, the output signals usually comprise a pair of voltage levels, one high and one low, on a line, and, when the unprimed signal output of a flip-flop is high in voltage and the primed signal output is low in voltage, the flipflop is true, while, for the reverse condition, the flip-flop is false; thus, flip-flop A1 is true when signal A is at the high voltage level and signal A is at the low voltage level.

On the other hand, the input signals to the flip-flops, which usually take the form of sharp pulses occuring at the trailing edge of a clock signal, i.e., at the end of a bit period, are designated by corresponding lower case letters with the associated number shown as a subscript. The input signal for setting the flip-flop is designated by a subscript l prefixing the lower case letter: thus, signals :1 b etc. The input signal for resetting the flip-flop is designated by a subscript 0 prefixing the lower case letter: thus, signals a b etc. These two signals are the only ones required to be specified for the R-S flipfiop; for the RS-T flip-flop, with which the invention will also be exemplified, the input elfective to change its state is designated by a subscript t prefixing the lower case letter: thus, signal b etc. For reference, the block diagram representation and truth tables corresponding to these flip-flops are shown in FIGURES 2 and 3. It is apparent that the R-S-T flip-flop with AND gates at its inputs and the R-S flip-flop with exclusive OR gates at its inputs are logical equivalents.

Those familiar with the art will readily recognize these flip-flops and that use may be made of any type, such as the D, T or JK described at pages 121 through 132 of the book Logical Design of Digital Computers by M. Phister, Jr., Wiley and Sons, Inc, New York, 1958, for either register or for any portion of the system Where bistability is required, without affecting the inventive concept. However, the structure of network will, of course, require modification in accordance with the logic (i.e., the characteristic equations) of the selected circuits.

Returning now to FIGURE 1, the function of bit counter register 20 is to count pulses of signal C and to generate, on its output lines, equal, sequential and cyclical signals P through P from its flip-flops P1 through P6, for which the process of generating each word will coincide. Register 20 cooperates with gates in network 10 to provide a binary counter of signal C pulses; only one of the output lines from register 20 at a time may be at the high potential for enabling gates in network 10. Register 20 responds to 6 sequential pulses of signal C and then recycles; thus, by noting the output of register 20, succeeding bit periods may be identified and network 10 be set up to provide the appropriate logic for generating the word. Also, register 20 is reset by start circuit 18 when the last word of the last cycle is generated.

The time period required to generate a word is designated a Word period; these are tallied by word counter register 21 as counts W through W each appearing as a unique combination of signals on the four conductors of line 31. Word counter register 21 advances in response to a period P, pulse and is reset to W, by start circuit 18.

Counters such as registers 20 and 21 are well known to be capable of providing the basic timing sequence which controls the activation of appropriate portions of equipment familiar in computer technology, such as the gates in network 10 in the present case.

Network 10 also serves to route control information in a manner appropriate to perform the desired word generation. Thus, presets of register A and matrix 12 are transferred from preset circuits 15 and 13, respectively (switches on the operators control panel, not shown in FIGURE 1) via lines 24 and 22, respectively, to network 10. The register A preset, as well as the different register B outputs each representing a word, are conveyed by lines 28 and 30 to register A where they are set up in flip-flops A1 through A4 at the appropriate bit periods. The register A outputs, designated A A A and A on line 32, feed into network 10, where they are arithmetically handled by matrix 12 to form a new word and set up through line 34 in register B. The generated word appears on output line 26 connecting to register B.

It has been pointed out that a reduced-length sequence of Words may be generated repetitively by this generator. This is accomplished by resetting register 21, utilizing words preset register 36 and line 37, at a specific number equal to or less than the maximum number of Words of which register 21 is capable (here, 15) and presetting register A preset 15 according to a specific word. As a result, the selected number of words starting with the specific word is repetitively generated on line 26.

In a similar fashion, the present system provides a means for generating a designated number of cycles of words if continuous operation of the generator is not desired. This comprises cycle counter register which, if reset at a specific count, by cycles preset register 38 and line 39, will provide the designated number of cycles of the sequence selected by register 21 and matrix 12. Although a maximum of 32 counts, D D D D on line 35, is shown for register 25, it should be understood that this is only illustrative since any number of counts may be arranged for by altering its stage content.

The invention, in one embodiment, provides a Word generator utilizing circuitry the operation of which may be represented as a system of linear equations. Considering, for example a requirement for a sequence of 15 different four-bit words, these may be provided, using a four-stage shift register, as the combinational states of flip-flops by regarding the voltages on corresponding outputs of the flip-flops.

Such a register may comprise four stages B1, B2, B3 and B4, operating in accordance with the tables shown in FIGURES 4, 5, 6 and 7. If the triggering equations for each flip-flop are derived from the tables, it will be found that they may be summarized in the form of the application equations written below the tables. The equation B1=B1EBB4 of FIGURE 4, for instance, signifies that the state of flip-flop Bl during the bit period will be defined by an exclusive OR (6)) connection of the outputs of flip-flops B1 and B4 during the next prior bit period; i.e., that flip-flop B1 will trigger true if the modulo 2 sum of the states of flip-flop B1 and B4 is one, i.e., if flip-flops B1 and B4 were priorly in different states, but will trigger false if the modulo 2 sum of these flipflops is zero, i.e., if flip-flops B1 and B4 were priorly in the same state. The corresponding triggering equations are b :B B '+B 'B and b =B B +B B The equation Bl:B1@B4 of FIGURE 5 is similarly interpreted except that the logical connective is not the exclusive OR but the EQUALS, signifying that flip-flop B1 will trigger true if flip-flop B1 and B4 were priorly in the same state but will trigger false if the states were different. The corresponding triggering equations are 15 :B,B +B 'B and b :B,B.;'+B,B The equations for flip-flops B2, B3 and B4 in FIGURES 4 and 5 simply indicate that the states of these flip-flops follow those of their predecessors, i.e., that the register is connected by network 10 as a shift register for the purposes of generating these word sequences. The corresponding triggering equations are I1 =B 15 23 b :B b :B [2 :3 and b ZB It will be noted that these sequences are m-sequences and complementary.

If the requirement is for a cyclic sequence of the following six different words l5, 7, 3, 9, 12, 14, it is indicated in FIGURE 8 that matrix 12 must provide connections represented as B1:B2$B4, 82:31, B3 132, B4=B3, and the register initially be set with one of the words in this sequence, such as the all-ones count 15. It is shown in this figure that the six-word sequence 1, 8, 4, 10, 5, 2 is also available from the same configuration of matrix 12 if its preset is with one of the words of this sequence. Additionally available from the same configuration of matrix 12 is the three-word sequence 6, 11, 13 if the shift register is preset with one of these words. In summary, the table of FIGURE 8 shows the cyclic sequences available from four-stage register B connected as a shift register and governed by the corresponding configuration of matrix 12, the register being preset with one of the sequence words.

Additionally, if matrix 12 connects register B as one other than a shift register, with appropriate initial set by register A preset 15 (FIGURE 1), other Word sequences would be made available. The table in FIGURE 9 indicates a few of these sequences and the corresponding logic configurations.

It will also be made apparent that, by utilizing register A preset 15 to provide an override, a reduced number of counts of a sequence is established by the initial set by matrix 12 preset 13. Thus, referring to FIGURE 4, for instance, if the generator output requirement is for seven cycles of just the counts 5, 10, 13, 6, 3 and 9 of the m-sequence shown, the preset of matrix 12 is established as represented by the equations accompanying the figure, the preset of register A is established at count 5, words preset register 36 is arranged to provide a cyclic count of six word periods by word counter register 21, and cycles pre set register 38 is arranged to provide seven cycles of operation in cycle counter register 25, which will then interrupt the energization of network 10 by clock signal source 14 via start circuit 18.

It should be noted from the above that there are provided four presets which establish the operating characteristics of the word generator: for register A (preset for matrix 12 (preset 13), for word counter register 21 (register 36) and for cycle counter register 25 (register 38). By appropriately combining these presets at the operators console, a remarkable word generating capability results; for instance, there may be arranged emission of the following:

l Preset 13 31 cycles of the eight words 12 through 9 of Figure Logic of Pig, 6.

The above operating features are more particularly illustrated in FIGURES 10a and 10b, which together form a schematic diagram depicting a generator of 4-bit words specifically set up to produce 15 words cyclically; the generator arrangement is represented by the equations shown below the diagram, which is the last entry in the table of FIGURE 9 and for which the binary counts are given in FIGURE 6.

It is seen that the settings for start circuit 18 and registers 36 and 38 originate with the operator. Start circuit 18 comprises a bistable state device, single-shot S1, which triggers the reset input to flip-flop S2: s =S Output S opens AND gate 90 in logical network 10 to pass signal C to all gates. In the interest of simplicity in the presentation of the figure, all connections for signal C are not shown nor is the term included in the equations, although it should be understood that, since, as already mentioned, preference is for a synchronous system, these connections are made and all equation terms are logically multiplied (logical AND) by signal C.

Bit counter register 20 comprises fiip flops P1 through P6 and is activated by the output of gate 90 to provide its sequential outputs. The register is reset to zero by signal S which is at the high level when the last word of the last cycle is generated. The logic in network 10 governing the operation of register 20 is as follows: p :P S 1p2 1 iPs= 2 inf- 3 1I5 4 1P6= 5 0P1:P1+S2 Signal P activates word counter register 21 to increase its count, thereby providing on its combined output lines 31 a decimal indication of the word of the sequence being generated. The decimal count is converted by converter 33 to signals on individual lines W through W according to the following logic:

The logic for generating the decimal counts will not be given here since it is considered to be taught in the Phister book already referenced.

The count, in decimal form, is compared in comparator 92 with the setting in words preset register 36, which comprises flip-flops R1, R2, R3 and R4 and, if there is equality, comparator 92 emits at period P a pulse on line 91, the input to cycle counter register 25 and on line 93. The comparison logic is:

Prcset 15 Register 36 Register 38 Any number 1-15 15 7 Any 0H5, l3, 4, 10,7,l1 6 1 12 8 31 parator 92, through line 93, gates comparator 94. The

logical equation for this activity is:

For the example in FIGURES 10a and 10!), matrix 12 comprises 16 AND gates arranged in four columns (vertical) of four rows (horizontal), each column associated with the unprinted output (FIGURE 2) of one of the flip-flops of register A and each row associated with the 1 input (FIGURE 3) of one of the fiipflo-ps of register B. Thus, the columns include AND gates: 40, 42, 44 and 46; 50, 52, 54 and 56; 60, 62, 64 and 66; and 70, 72, 74 and '76. The rows include AND gates: 40, 50, 60 and 70; 42, 52, 62 and 72; 44, 54, 64 and 74; and 46, S6, 66 and 76. The outputs of the gates of a row are connected to an OR gate 71a, 71b, 71c or 714, thus, gates 40, 50, 60 and 70 are connected to OR gate 71a, and the OR gate output leads to the 1 input of the register B flip-flop. The matrix 12 AND gates have two inputs: a column input fed by the outputs of AND gates 80, 82, 84 and 86 and individual switch inputs through line 22 from preset circuit 13. AND gates 80, 82, 84 and 86 are opened to the unprlmed outputs of the flip-flops of register A, respectively, by bit period signals P P P and P respectively, generated by bit counter register 20. The inputs to register A, gated at the bit periods shown, consist of the unprimecl outputs of register B (via line 28) gated by signal P through AND gates 81, 83, and 87 and switch inputs from preset circuit 15 (via line 24) through OR gates 63, 65, 67 and 69 at their set inputs and 73, 75, 77 and 79 at their reset inputs. Additionally, the A register reset inputs are activated by bit period signal P; through gates 63, 65, 67 and 69.

In brief, in view of the system of logic presentation already given, the triggering connections of registers A and B made by logical network 10 are as follows:

The output signals on line 26 are, of course, B B B and B and should be sampled at period P From the foregoing discussion, it should be apparent that these triggering equations operate to accomplish the logic given by the application equations shown in FIG- URE 6.

In order that there be an indication at the operators console that the number of cycles of the present sequence has been generated, output signal S is transmitted thereto. If the console is part of a computer system, this signal may be used to step the computer program unit through its flow diagram to pick up the next sequence and the required presets.

With regard to the operation of the system of FIG- URES a and 101), it will be presumed that words preset register 36 is storing the number 9, that cycles preset register 38 is storing the number 21, that register A preset is at 14, that matrix 12 preset 13 corresponds to the logic given in FIGURE 6 and that hit counter register 20, word counter register 21 and cycle counter register 25 are reset. Referring to FIGURE 6, it is seen that these settings indicate that 21 cycles of the following nine words be generated: 14, 11, 9, 10, 5, 2, 3, 15, 7.

Triggering of single shot S1 at the operators console by means of, for instance, a start button, resets flipfiop S2 to open gate 90 and remove the reset (signal S to hit counter register 20, word counter register 21 and cycle counter register 25. Receipt of signal C causes bit counter register 20 to sequence through its six counts. At each count P a pulse is entered into word counter register 21 and, if there is equality between the content of register 21 and Words preset register 36, a pulse is entered during this bit period into cycle counter register 25. The table of FIGURE 11 indicates some of the system activity corresponding to this example; in the table, decimal numerals are indicated within a pair of horizontal dashes.

Some of the equipment shown in block diagram form has not been detailed here. Thus, the gates, converter 34 and comparators 92 and 94 are considered to be sufficiently known from their equations to require no further discussion.

While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that the foregoing and other changes in the form and details may be made therein without departing from the spirit and scope of the invention.

What is claimed is:

1. A word generator, comprising:

first and second registers each capable of storing a word;

a network for transfer of words between said registers;

first preset means to establish the words transferred by said network in a sequence;

second preset means to establish the first word in the sequence;

third preset means to establish the number of words in the sequence; and

fourth preset means to establish the number of sequences,

2. The generator of claim 1 wherein said registers comprise a plurality of stages and said network includes a plurality of gates at the input to the stages of said second registers and said first preset means includes switch means for selectively activating the gates at the input to the stages of said second register.

3. The generator of claim 2 wherein said network includes a plurality of gates at the inputs to the stages of said first register and said second preset means includes switch means for activating the gates at the inputs to the stages of said first register in accordance with a desired first word; and

means to select between the switch means of said second preset means and said second register for transfer to said first register.

4. The generator of claim 3 wherein said third preset means comprises a third register set up with the number of words in a sequence,

a counter for tallying the number of words transferred and a comparator responsive to said third register and said counter to emit an equality signal for energizing the gates of said network at the inputs to the stages of said first register.

5. The generator of claim 3; and

a start circuit for initiating the operation of said network.

6. The generator of claim 5 wherein said fourth preset means comprises a fourth register set up with the number of sequences;

a counter for tallying the number of sequences generated and a comparator responsive to said fourth register and said counter to emit an equality signal for controlling said start circuit.

7. The generator of claim 6 wherein said start circuit includes a bistable state circuit triggerable into one of its states at initiation of the operation of said network and into the other of its states by the equality signal emitted by said comparator of said fourth preset means.

References Cited UNITED STATES PATENTS 3,046,545 7/ 1962 Westerfield 235-181 3,051,784 8/1962 Neumann 340-1461 3,076,956 2/1963 Hagan et al. 340-1725 3,114,130 12/ 1963 Abramson 340-1461 3,119,097 1/1964 Tullos 340-168 3,128,449 4/1964 Armstrong 340-146.] 3,155,818 11/1964 Goetz 340-1461 3,162,837 12/1964 Meggitt 340-1461 3,283,131 11/1966 Carbrey 235-164 2,903,676 9/ 1959 Ostendorf 340-168 2,951,230 8/1960 Cadden 340-168 3,119,071 1/1964 Euler et al. 328-187 PAUL J. HENON, Acting Primary Examiner. J. P. VANDENBURG, Assistant Examiner, 

1. A WORD GENERATOR, COMPRISING: FIRST AND SECOND REGISTERS EACH CAPABLE OF STORING A WORD; A NETWORK FOR TRANSFER OF WORDS BETWEEN SAID REGISTERS; FIRST PRESET MEANS TO ESTABLISH THE WORDS TRANSFERRED BY SAID NETWORK IN A SEQUENCE; SECOND PRESET MEANS TO ESTABLISH THE FIRST WORD IN THE SEQUENCE; THIRD PRESET MEANS TO ESTABLISH THE NUMBER OF WORDS IN THE SEQUENCE; AND FOURTH PRESET MEANS TO ESTABLISH THE NUMBER OF SEQUENCES. 